1. Field of the Invention
Systems and methods consistent with the present invention relate to a memory device, and more particularly, to a multi-channel flash memory system using a plurality of flash memory chips, the system capable of increasing the overall bandwidth by storing to-be-recorded data independently for each channel according to an interleaving process, a host system providing the to-be-recorded data to the flash memory system, and a programming method performed by the host system and the flash memory system.
2. Description of the Related Art
Flash memories, which are non-volatile memories capable of electrically deleting or re-recording data, are classified into a NOR type and a NAND type according to how cells and bitlines are connected to each other.
NAND flash memories, which are storage areas for storing information, include memory cell arrays. A memory cell array includes a plurality of cell strings (which are also called NAND strings). In order to store data in a memory cell array of a flash memory or read data therefrom, the flash memory is provided with a page register circuit. As is well known to those of ordinary skill in the art, memory cells of a NAND flash memory are erased and programmed using a Folwer-Nordheim (F-N) tunneling current.
In order to store data in the memory cell array of the flash memory, first, a write command is given to the flash memory, and addresses and data are consecutively input to the flash memory. Generally, data, which is to be programmed, is sequentially transmitted to a page register circuit on a byte-by-byte basis or on a word-by-word basis. When the to-be-programmed data corresponding to one page of data is completely loaded to the page register circuit, data preserved in the page register circuit is programmed simultaneously in the memory cell array (i.e., memory cells of a selected page) according to a programming command.
In the related art, in order to increase the storage capacity of a flash memory, a multi-channel flash memory system using a plurality of flash memory chips has been proposed.
FIG. 1 is a block diagram of a configuration of a related art 2-channel flash memory system 20 using a plurality of flash memory chips. Referring to FIG. 1, the related art 2-channel flash memory system 20 includes a host interface unit 21 receiving to-be-recorded data by means of communication with a host 10, first and second buffers 22 and 23 storing received data, a control unit 24, and first through fourth flash memory chips 25, 26, 27, and 28. The first and second flash memory chips 25 and 26 constitute a first channel unit CH1, and the third and fourth flash memory chips 27 and 28 constitute a second channel unit CH2.
FIG. 2 illustrates a sequence in which the data to be recorded in the flash memory system 20 shown in FIG. 1 is transmitted. FIG. 3 is a timing diagram illustrating a recording operation performed in each of the channel units CH1 and CH2 of the flash memory system 20 shown in FIG. 1.
The host 10 divides the to-be-recorded data into several pieces of page data of predetermined size and sequentially transmits the divided page data to the first and second channel units CH1 and CH2. Referring to FIG. 2, the to-be-recorded data is divided into several pieces of 8 Kbyte page data.
The transmitted page data pieces are sequentially stored in the first and second buffers 22 and 23 according to the sequence in which the page data pieces are transmitted. Then, the page data pieces stored in the first and second buffers 22 and 23 are input to the flash memory chips of the first and second channel units CH1 and CH2, respectively. More specifically, the control unit 24 instructs a writing command to a first flash memory chip 25 of the first channel unit CH1 and a third flash memory chip 27 of the second channel unit CH2. In response to the writing command, an address and first and second page data P1 and P2 stored in the first and second buffers 22 and 23 are loaded into page registers included in the first and third flash memory chips 25 and 27. This loading operation is referred to as a setup operation. The time required to perform the setup operation is referred to as a setup time.
After the setup operation with respect to the first and third flash memory chips 25 and 27 is completed, the control unit 24 instructs a programming command to the first and third flash memory chips 25 and 27 so that the page data P1 and P2 loaded in the page registers be programmed in memory cell arrays included in first and third flash memory chips 25 and 27. This process is referred to as a programming operation. The time required to perform the programming operation is referred to as a programming time.
Also, the control unit 24 instructs a writing command to a second flash memory chip 26 of the first channel unit CH1 and a fourth flash memory chip 28 of the second channel unit CH2 so that third and fourth page data P3 and P4 are loaded into page registers included in the second and fourth flash memory chips 26 and 28, respectively.
Then, the control unit 24 determines whether the programming operation with respect to the first and third flash memory chips 25 and 27, that is, the storage of the first and second page data P1 and P2 in the memory cell arrays, has been completed, using ready/busy (B/D) signals of the first and third flash memory chips 25 and 27. If it is determined that the programming operation has been completed, the control unit 24 instructs a writing command to the first and third flash memory chips 25 and 27 to load fifth and sixth page data P5 and P6 into the page registers included in the first and third flash memory chips 25 and 27.
However, in such a related art flash memory system, when there is a difference between the programming times of channels, a channel having a slower programming time affects a channel having a faster programming time. Referring to FIG. 3, when the programming time of each of the first and second flash memory chips 25 and 26 of the first channel unit CH1 is 200 μs, and the programming time of each of the third and fourth flash memory chips 27 and 28 of the second channel unit CH2 is 400 μs, the slower programming time of the flash memory chips of the second channel unit CH2 affects the faster programming time of the flash memory chips of the first channel unit CH1. In other words, a setup operation for the fifth page P5 that is performed after completion of the programming of the first page data P1 in the first flash memory chip 25 can actually occur after completion of the programming with respect to the third flash memory chip 27 of the second channel unit CH2 having a programming time slower than that of the first channel unit CH1. This is because the single control unit 24 controls both the programming operations with respect to the flash memory chips of the first and second channel units CH1 and CH2.
Hence, although the first channel unit CH1 having a faster programming time has completed a programming operation for page data, it cannot perform setup and programming operations for the next page data, and time blanks as indicated by reference symbols A and B are generated. Thus, the bandwidth cannot be sufficiently utilized.
As illustrated in FIG. 2, in the related art multi-channel flash memory system 20, to-be-recorded data is sequentially transmitted in such a way that the first page data P1 is allocated to the first channel unit CH1, the second page data P2 is allocated to the second channel unit CH2, the third page data P3 is allocated to the first channel unit CH1, and the fourth page data P4 is allocated to the second channel unit CH2. Accordingly, when the programming time of the first channel unit CH1 is different from that of the second channel unit CH2, one of the first and second channel units CH1 and CH2 that has a slower programming time affects the other one that has a faster programming time.